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FALL 2018 | MS| EE|GRE 331(Q-168/ V-163/AWA-4.5) |CGPA 76%| DTU
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preyeshdalmia Offline
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preyeshdalmia Offline
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FALL 2018 | MS| EE|GRE 331(Q-168/ V-163/AWA-4.5) |CGPA 76%| DTU
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MS in EE with specialization in VLSI (Proclivity towards both Front end and back end design)

Profile Link : http://www.edulix.com/unisearch/user.php?uid=339371
Work Experience:
Synopsys, India : June 2016- Ongoing : 2 years Work ex by Fall 2018
Research and Development Engineer for the Vertical Solutions team of ZEBU the Functional Verification tool of the Verification group of Synopsys.
Transactor Devolopment, RTL design, C++, Protocol-DP, HDMI, UART,I2C , Functional Verification Cycle

Summer Intern:
Cadence Design Systems:
Was part of the Product Engineering department of their Static timing Anaylsis tool Tempus (TSS). Worked on creating models for low voltage library binding for different instances in the design. Learnt about the various stages involved in timing analysis and the timing reports generated by Tempus tool.

Research intern:
Defence Research and Development Organisation (DRDO): Research intern
Working under Mr. Fahim Khan in the domain of digital circuit design and FPGA implementation.


Industrial Training:
Panasonic AVC India Pvt Ltd
Acquired knowledge of LED TV Manufacturing line in the plant
Learnt about the Power and Main boards in the AIP section.

Research and Project Experience:

1) Novel Quaternary Signed Digit Adder based High Speed Vedic Multiplier : ASIC
Selected to be presented in VLSI Design Conference 2018

2) An FPGA based floating point Gauss Seidel iterative solver : Algorithm Optimization and High Speed Hardware Implementation. Submitted in INDICON. Results Expected Mid October

3) Fast Combinational Architecture for a Vedic Divider: Modified Vedic Algorithm: Submitted in INDICON. Results Expected Mid October

4) FPGA implementation of Improved Alpha-Beta Pruning and Search Depth Optimized Iterative Deepening Algorithm for Tic-Tac-Toe : Algorithm Optimization and Design of Game Machine

5) Elliptical Cryptography Co-processor : algorithm Implementation and Optimization in Verilog : FPGA implementation

6) Design and Implementation of 32 bit-Negative Logic Quaternary Adder: Carry Free addition Implemented

Position of Responsibilities:
1. Founder and Researcher, VLSI Research Group, Delhi Technological University: Student Initiative (2 2015-Present)
Currently, has a strength of 25 students. Overlooking All Projects undertaken by this Group. Officially recognized by the College.

2. Team lead DCE Placement Fundas (2015-2016)
Conducted and Organized classes for Pre-Final year placements pertaining to Both Technical and Non-Technical Fields.

3. VLSI SIG head, and Project Coordinator - Society of Robotics, DTU (2014-2016)

4. Columnist/Member of publication team of DTU TIMES(official publication of college), CASRAE DTU, SR DTU,
SHOPILINE.COM, E-cell DTU, IEEE-DTU

List of universities I am targeting


1. University of California, Berkeley
2. University of Illinois, Urbana Champaign
3. Georgia Institute of Technology
4. University of Michigan, Ann Arbor
6. Carnegie Melon University
6. University of Texas, Austin
7. Purdue University
8. University of Southern California
9. Texas A&M University, College Station
10. University of California, Santa Barbara
11. University of California, San Diego
12. University of Pennsylvania
13. North Carolina State University
14. Columbia University
15. Ohio State University
16. Pennsylvania State University
17. Arizona State University


Requesting profile Evaluation for the above-mentioned Universities.

Or any University suggestions you guys might have. That I might have overlooked

Tagging seniors for their kind help Smile
ChinmayNKumar
jules20
sajinsabu
supernovapavan
harikkrishna
(This post was last modified: 09-19-2017 07:19 PM by preyeshdalmia.)
09-12-2017 07:01 PM
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FALL 2018 | MS| EE|GRE 331(Q-168/ V-163/AWA-4.5) |CGPA 76%| DTU - preyeshdalmia - 09-12-2017 07:01 PM

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