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|Details of preyesh|
|Real Name||Preyesh Dalmia|
|Specialization||VLSI, Digital Design, Computer Architecture|
|Term and Year||Fall - 2018|
|Standardized Test Scores|
|University/College||Delhi Technological University|
|Department||Electronics and Communication|
|Experience and Publications|
|Industrial Experience||0 Years, 0 Months|
|Research Experience||0 Years, 0 Months|
|Internship Experience||0 Years, 0 Months|
|Applied Visa Type||Still To Apply|
|Visa Consulate City|
|Type of Finance Docs||Not Applicable|
|Type of Financial Aid||Not Applicable|
|Other Miscellaneous Details|
Synopsys, India : June 2016- Ongoing : 2 years Work ex by Fall 2018
Research and Development Engineer for the Vertical Solutions team of ZEBU the Functional Verification tool of the Verification group of Synopsys.
Transactor Devolopment, RTL design, C++, Protocol-DP, HDMI, UART,I2C , Functional Verification Cycle
Cadence Design Systems:
Was part of the Product Engineering department of their Static timing Anaylsis tool Tempus (TSS)
Worked on creating models for low voltage library binding for different instances in the design.
Learnt about the various stages involved in timing analysis and the timing reports generated by Tempus tool.
Defence Research and Development Organization (DRDO): Research intern
Working under Mr. Fahim Khan in the domain of digital circuit design and FPGA implementation.
Working on Implementation of 3rd degree curves showing behaviour of various parameters of Metal oxide.
Panasonic AVC India Pvt Ltd
Acquired knowledge of LED TV Manufacturing line in the plant
Learnt about the Power and Main boards in the AIP section.
Research and Project Experience:
1) Novel Quaternary Signed Digit Adder based High Speed Vedic Multiplier : ASIC
Submitted in VLSI Design Conference. Results Expected Mid September
2) An FPGA based floating point Gauss Seidel iterative solver : Algorithm Optimization and High Speed Hardware Implementation. Submitted in INDICON. Results Expected Mid October
3) Fast Combinational Architecture for a Vedic Divider: Modified Vedic Algorithm: Submitted in INDICON. Results Expected Mid October
4) FPGA implementation of Improved Alpha-Beta Pruning and Search Depth Optimized Iterative Deepening Algorithm for Tic-Tac-Toe : Algorithm Optimization and Design of Game Machine
5) Elliptical Cryptography Co-processor : ALogorithm Implementation and Optimization in Verilog : FPGA implementation
6) Design and Implementation of 32 bit-Negative Logic Quaternary Adder: Carry Free addition Implemented
Position of Responsibilities:
1. Founder and Researcher, VLSI Research Group, Delhi Technological University : Student Initiative (2 2015-Present)
Currently has a strength of 25 students. Overlooking All Projects undertaken by this Group. Officialy recognized by the College.
2. Team lead DCE Placement Fundas (2015-2016)
Conducted and Organized classes for Pre-Final year placements pertaining to Both Technical and Non-Technical Fields.
3. VLSI SIG head, and Project Coordinator - Society of Robotics, DTU (2014-2016)
4. Columnist/Member of publication team of DTU TIMES(official publication of college), CASRAE DTU, SR DTU,
SHOPILINE.COM, E-cell DTU, IEEE-DTU
|University details not updated|